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rev 1.0 6/20/00 characteristics subject to change without notice. 1 of 21 www.xicor.com preliminary information programmable analog x9430 dual digitally controlled potentiometer (xdcp ? ) with operational amplifier features two cmos voltage operational amplifiers two digitally controlled potentiometers can be combined or used separately amplifiers ?low voltage operation ?v+/v- = 2.7v to 5.5v ?rail-to-rail cmos performance ?1mhz gain bandwidth product digitally controlled potentiometer ?dual 64 tap potentiometers ?r total = 10k? ?spi serial interface ?v cc = 2.7v to 5.5v description the x9430 is a monolithic cmos ic that incorporates two operational amplifiers and two nonvolatile digitally controlled potentiometers. the amplifiers are cmos differential input voltage operational amplifiers with near rail-to-rail outputs. all pins for the two amplifiers are brought out of the package to allow combining them with the potentiometers or using them as com - plete stand-alone amplifiers. the digitally controlled potentiometers consist of a series string of 63 polycrysta lline resistors that behave as standard integrated circuit resistors. the spi serial port, common to both pots, allows the user to program the connection of the wiper output to any of the resistor nodes in the series string. the wiper position is saved in the on board e2 memory to allow for nonvolatile res - toration of the wiper position. a wide variety of applications can be implemented using the potentiometers and the amplifiers. a typical appli - cation is to implement the amplifier as a wiper buffer in circuits that use the potentiometer as a voltage refer - ence. the potentiometer can also be combined with the amplifier yielding a digitally programmable gain amplifier or programmable current source. block diagram v out1 control and cs sck so si a1 a0 + ? memory v cc v ni0 v+ v? r w0 v ss v out0 + ? v ni1 v inv1 v inv0 r h0 r l0 r w1 r l1 r h1 wcr1 wcr0 wp hold n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
x9430 ? preliminary information characteristics subject to change without notice. 2 of 21 rev 1.0 6/20/00 www.xicor.com pin descriptions host interface pins serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses and data to be written to the device are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9430. chip select ( cs ) when cs is high, the x9430 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) th e device will be in the standby state. cs low enables the x9430, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hardware write protect input wp the wp pin when low prevents nonvolatile writes to the wiper counter register. hold ( hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume com - munication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 ?a 1 ) the address inputs are used to set the least significant 2 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9430. a maximum of 4 devices may occupy the spi serial bus. potentiometer pins 1 r h (r h0 ?r h1 ), r l (r l0 ?r l1 ) the r h and r l inputs are equivalent to the terminal connections on either end of a mechanical potentiom - eter. r w (r w0 ?r w1 ) the wiper output is equivalent to the wiper output of a mechanical potentiometer. amplifier and device pins amplifier input voltage v ni (0,1) and v inv (0,1) v ni and v inv are inputs to the noninverting (+) and inverting (-) inputs of the operational amplifiers. amplifier output voltage v out (0,1) v out is the voltage output pin of the operational ampli - fier. analog supplies v+, v- the analog supplies v+, v- are the supply voltages for the xdcp analog section and the operational amplifi - ers. system supply v cc and ground v ss the system supply v cc and its reference v ss is used to bias the interface and control circuits. 1. alternate designations for r h , r l , r w are v h , v l , v w
x9430 ? preliminary information characteristics subject to change without notice. 3 of 21 rev 1.0 6/20/00 www.xicor.com pin configuration pin names principles of operation the x9430 is an integrated microcircuit incorporating two digitally controlled potentiometers, two operational amplifiers and their associated registers and counters; and the serial interface logic providing direct communica - tion between the host and the digitally controlled potentiometers. serial interface the x9430 supports the spi interface hardware con - ventions. the device is accessed via the si input with data clocked in on the rising edge of sck. cs must be low and the hold and wp pins must be high dur - ing the entire operation. v cc r l0 r h0 wp a1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v+ v out0 v ni0 v inv0 a0 s0 hold sck v inv1 v ni1 soic x9430 v ss r w0 14 13 11 12 cs r l1 r h1 r w1 v out1 v- si v- v inv0 v ni0 hold so sck 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 cs v cc r w0 tssop x9430 v+ v out0 11 12 a 0 v out1 v ni1 v inv1 r l0 r h0 v ss r w1 r h1 r l1 a 1 si wp 15 14 13 symbol description sck serial clock si serial input so serial output a0-a1 device address cs chip select hold hold r h0 ?r h1 , r l0 ?r l1 potentiometers (terminal equivalent) r w0 ?r w1 potentiometers (wiper equivalent) v ni(0,1) , v inv(0,1) amplifier input voltages v out0, v out1 amplifier outputs wp hardware write protection v+,v- analog and voltage amplifier supplies v cc system/digital supply voltage v ss system ground
x9430 ? preliminary information characteristics subject to change without notice. 4 of 21 rev 1.0 6/20/00 www.xicor.com potentiometer/array description the x9430 is comprised of two resistor arrays and two operational amplifiers. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a volatile wipe r counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. operational amplifier the voltage operational amplifiers are cmos rail-to-rail output general purpose amplifiers. they are designed to operate from dual () power supplies. the amplifiers may be configured like any standard amplifier. all pins are externally available to allow connection with the potentiometers or as stand alone amplifiers. detailed block diagram v out (0,1) (dr0-dr3) 0,1 control and cs sck so si a1 a0 v h (0,1) v l (0,1) wp v w (0,1) v n (0,1) + ? wcr 0,1 (dr0-dr3) 0,1 v inv (0,1) v ss v cc hold memory wcr0 wcr1 (one of 2 circuits) write in process the contents of the data registers are saved to nonvol - atile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write opera - tion can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions and programming identification (id) byte the first byte sent to the x9430 from the host, follow - ing a cs going high to low, is called the identifica - tion byte. the most significant four bits of the slave address are a device type identifier, for the x9430 this is fixed as 0101[b] (refer to figure 1).
x9430 ? preliminary information characteristics subject to change without notice. 5 of 21 rev 1.0 6/20/00 www.xicor.com the two least significant bits in the id byte select one of four devices on the bus. th e physical device address is defined by the state of the a 0 -a 1 input pins. the x9430 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9430 to successfully continue the command sequence. the a 0 ?a 1 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the slave byte must be set to 0. figure 1. identification byte format instruction byte the next byte sent to the x9430 contains the instruc - tion and register pointer information. the four most sig - nificant bits are the instruction. the next four bits point to one of the wcrs of the two pots, and when applica - ble, they point to one of four associated data registers. the format is shown below in figure 2. figure 2. instruction byte format the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instructi on is issued. the last bit (p 0 ) selects which one of the two potentiometers is to be affected by the instruction. four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. the basic sequence of the tw o byte instructions is illus - trated in figure 3. these two-byte instructions exchange data between a wiper counter register and one of the four data registers associated with each. a transfer from a data register to a wiper counter register is essentially a write to a static ram. the response of the wiper to this action will be delayed t wrl . a transfer from the wiper counter register (current wiper position) to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the poten - tiometers and one of their associated registers. five instructions require a three-byte sequence to com - plete. these instructions transfer data between the host and the x9430; either between the host and one of the data registers or directly between the host and the wiper counter and registers. these instructions are: 1) read wiper counter register, read the current wiper position of the selected pot 2) write wiper counter register, i.e. change current wiper position of the selected pot; 3) read data register, read the con - tents of the selected nonvolatile register; 4) write data register, write a new value to the selected data register; 5)read status, returns the contents of the wip bit which indicates if an internal write cycle is in progress. the sequence of these operations is shown in figure 4 and figure 5. the final command is increment/decrement. it is differ - ent from the other commands, because it?s length is indeterminate. once the co mmand is issued, the mas - ter can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the se lected wiper will move one resistor segment towards the v h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l terminal. a detailed illustrati on of the sequence and timing for this operation are shown in figure 6 and figure 7. 1 00 00 a1a0 device type identifier device address 1 i1 i2 i3 i0 r1 r0 0 p0 wcr select register select instructions
x9430 ? preliminary information characteristics subject to change without notice. 6 of 21 rev 1.0 6/20/00 www.xicor.com figure 3. two byte command sequence figure 4. three-byte command sequence (write) figure 5. three-byte command sequence(read) figure 6. increment/decrement command sequence 010100a1a0 i3 i2 i1 i0 r1 r0 0 p0 sck si cs 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 0 p0 sck si 0 0 d5 d4 d3 d2 d1 d0 cs 00 0101 a1a0 i3 i2 i1 i0 r1 r0 0 p0 sck si cs 00 s0 0 0 d5 d4 d3 d2 d1 d0 don?t care 010100a1a0 i3 i2 i1 i0 0 0 p0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs
x9430 ? preliminary information characteristics subject to change without notice. 7 of 21 rev 1.0 6/20/00 www.xicor.com figure 7. increment/decrement timing sck si v w inc/dec cmd issued t wrid v out register operation both digitally controlled potentiometers share the serial interface and share a common architecture. each potentiometer is associated with a wiper counter regis - ter (wcr), and four data re gisters. figure 8 illustrates the control, registers, and system features of the device. figure 8. system block diagram wiper counter (wcr) and analog control registers (acr) the x9430 contains two wiper counter registers, one for each xdcp. the wiper counter register is equivalent to a serial-in, parallel-out counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wiper counter register can be altered in four ways: it may be written directly by the host via the write wcr instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers (dr) via the xfr data register instruction (parallel load); it can be modi - fied one step at a time by the increment/decrement instruction (wcr only). finally, it may be loaded with the contents of its associated data register zero (r0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9430 is powered-down. although the registers are automatically loaded with the value in r0 upon power-up, it should be noted this may be different from the value present at power-down. data registers (dr) each potentiometer has four nonvolatile data registers (dr). these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of these registers is a nonvolatile operation and w ill take a maximum of 10ms. if the application does not require storage of multiple set - tings for the potentiometer, these registers can be used as regular memory locations that could store system parameters or user preference data. v out (0,1) (dr0-dr3) 0,1 control and cs sck so si a1 a0 v h (0,1) v l (0,1) wp v w (0,1) v n (0,1) + ? wcr 0,1 v inv (0,1) v ss v cc hold memory wcr0 wcr1 detailed block diagram
x9430 ? preliminary information characteristics subject to change without notice. 8 of 21 rev 1.0 6/20/00 www.xicor.com register descriptions and memory map memory map wiper counter register (wcr) wp0-wp5 identify wiper position. data registers (dr, r0-r3) wcro wcr1 dr0 dr0 dr1 dr1 dr2 dr2 dr3 dr3 0 0 wp5 wp4 wp3 wp2 wp1 wp0 (volatile) (lsb) wiper position or user data (nonvolatile) instruction format notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the wiper counter register (3) ?i?: stands for the increment operation, si held high during active sck phase (high). (4) ?d?: stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) read the contents of the wiper counter register pointed to by p 1 -p 0 write wiper counter register (wcr) write new value to the wiper counter register pointed to by p 1 -p 0 read data register (dr) read the contents of the register pointed to by p 1 -p 0 and r 1 -r 0 write data register (dr) write new value to the register pointed to by p 1 -p 0 and r 1 -r 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9430 on so) cs rising edge 0 1 0 1 0 0 a 1 a 0 1 0 0 1 0 0 0 p 0 0 0 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 0 1 0 1 0 0 a 1 a 0 1 0 1 0 0 0 0 p 0 0 0 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr/wcr addresses data byte (sent by x9430 on so) cs rising edge 0 1 0 1 0 0 a 1 a 0 1 0 1 1 r 1 r 0 0 p 0 0 0 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr/wcr addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 0 1 0 1 0 0 a 1 a 0 1 1 0 0 r 1 r 0 0 p 0 0 0 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0
x9430 ? preliminary information characteristics subject to change without notice. 9 of 21 rev 1.0 6/20/00 www.xicor.com transfer data register (dr) to wiper counter register (wcr) transfer the contents of th e register pointed to by r 1 -r 0 to the wcr transfer wiper counter register (wcr) to data register (dr) transfer the contents of the wcr to the register pointed to by r 1 -r 0 increment/decrement wiper counter register (wcr) enable increment/decrement of the wcr pointed to by p 1 -p 0 global transfer data register (dr) to wiper counter register (wcr) transfer the contents of all four data registers pointed to by r 1 -r 0 to their respective wcr global transfer wiper counter register (wcr) to data register (dr) transfer the contents of all wcrs to their respective data registers pointed to by r 1 -r 0 read status returns the contents of the wip bit which indicates if an inte rnal write cycle is in progress cs falling edge device type identifier device addresses instruction opcode dr/wcr addresses cs rising edge 0 1 0 1 0 0 a 1 a 0 1 1 0 1 r 1 r 0 0 p 0 cs falling edge device type identifier device addresses instruction opcode dr/wcr addresses cs rising edge high-voltage write cycle 0 1 0 1 0 0 a 1 a 0 1 1 1 0 r 1 r 0 0 p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on sda) cs rising edge 0 1 0 1 0 0 a 1 a 0 0 0 1 0 x x 0 p 0 i/ d i/ d . . . . i/ d i/ d cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 0 1 0 1 0 0 a 1 a 0 0 0 0 1 r 1 r 0 0 0 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 0 1 0 1 0 0 a 1 a 0 1 0 0 0 r 1 r 0 0 0 cs falling edge device type identifier device addresses instruction opcode wiper addresses data byte (sent by x9430 on so) cs rising edge 0 1 0 1 0 0 a 1 a 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 w i p p 0 : 0-wcr0, 1-wcr1
x9430 ? preliminary information characteristics subject to change without notice. 10 of 21 rev 1.0 6/20/00 www.xicor.com absolute maximum ratings temperature under bias ....................?65 c to +135 c storage temperature .........................?65 c to +150 c voltage on sck, scl or any address input with respect to v ss ........... ?1v to +7v voltage on v+ (referenced to v ss ) ........................ +7v voltage on v- (referenced to v ss ) .......................... -7v (v+) ? (v-).............................................................. 10v any v h .................................................................... v+ any v l ...................................................................... v- lead temperature (soldering, 10 seconds)........ 300 c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli - ability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?40 c +85 c device supply voltage (v cc ) limits x9430 5v 10% x9430-2.7 2.7v to 5.5v potentiometer characteristics (over recommended operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to deter mine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti - ometer. it is a measure of the error in step size. (3) mi = rtot/63 or (r h ?r l )/63, single pot (=lsb) (4) individual array resolutions symbol parameter limits test conditions min. typ. max. unit r total end to end resistance ?20 +20 % power rating 50 mw 25 c, each pot i w wiper current ?3 +3 ma r w wiper resistance 40 100 ? v+ = 5v, v- = -5v, i w = 3ma 100 250 ? v+ = 2.7v, v- = -2.7v, i w = 1ma vv+ voltage on v+ pin x9430 +4.5 +5.5 v x9430-2.7 +2.7 +5.5 vv- voltage on v- pin x9430 -5.5 -4.5 v x9430-2.7 -5.5 -2.7 v term voltage on any r h or r l pin v- v+ v noise -100 dbv ref: 1v resolution (4) 1.6 % absolute linearity (1) ?1 +1 mi (3) v w(n)(actual) ?v w(n)(expected) relative linearity (2) ?0.2 +0.2 mi (3) v w(n + 1) ?[v w(n) + mi ] temperature coefficient of r total 300 ppm/c ratiometric temperature coefficient 20 ppm/c
x9430 ? preliminary information characteristics subject to change without notice. 11 of 21 rev 1.0 6/20/00 www.xicor.com amplifier electrical characteristics (over the recommended operating conditions unless otherwise specified.) v+ and v- (5v to 3v) are the amplifier power supplies. the amplifiers are specified with dual power supplies. v cc and v ss are the logic supplies. all ratings are over the temperature range for the industrial (-40 to + 85c) and commercial (0 to 70c) versions of the part unless specified differently. symbol parameter condition industrial commercial unit min. typ. max. min. typ. max. v os input offset voltage v+/v- 3v to 5v 1 3 1 2 mv tc vos input offset voltage temp. coefficient v+/v- 3v to 5v -10 -10 v/c i b input bias current v+/v- 3v to 5v 50 50 pa i os input offset current v+/v- 3v to 5v 25 25 pa cmrr common mode rejection ratio v cm = -1v to +1v 70 70 db psrr power supply rejection ratio v+/v- 3v to 5v 70 70 db v cm input common mode voltage range t j = 25c v- v+ v- v+ v a v large signal voltage gain v o = -1v to + 1v 30 50 30 50 v/mv v o output voltage swing v- v+ +0.1 -.15 +0.1 -.15 v v i o output current v+/v- = 5.5v v+/v- = 3.3v 50 30 50 30 ma ma i s supply current v+/v- = 5.0v 3 3 ma v+/v- = 3.0v 1.5 1.5 ma gb gain-bandwidth prod r l = 100k, c l = 50pf 1.0 1.0 mhz sr slew rate r l = 100k, c l = 50pf 1.5 1.5 v/sec m phase margin r l = 100k, c l = 50pf 80 80 deg.
x9430 ? preliminary information characteristics subject to change without notice. 12 of 21 rev 1.0 6/20/00 www.xicor.com potentiometer d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing symbol parameter limits test conditions min. typ. max. unit i cc1 v cc supply current (active) 400 a f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (nonvolatile write) 1 ma f sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 1 a sck = si = v ss , addr. = v ss i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?0.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per register data retention 100 years symbol test typ. max. unit test conditions c out (5) output capacitance (so) 8 pf v out = 0v c in (5) input capacitance (a0, a1, si, wp , hold and sck) 6 pf v in = 0v c l | c h | c w potentiometer capacitance 10/10/ pf symbol parameter max. unit t pur (6) power-up to initiation of read operation 1 ms t puw (6) power-up to initiation of write operation 5 ms a.c. test conditions notes: (5) this parameter is periodically sampled and not 100% tested. (6) t pur and t puw are the delays required from the time the third (last) power supply (v cc , v+ or v-) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. (7) the power-up order of power supplies are v cc , v+ and v-. spice macro model input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 c w r total r h r l c h r w c l
x9430 ? preliminary information characteristics subject to change without notice. 13 of 21 rev 1.0 6/20/00 www.xicor.com ac timing high-voltage write cycle timing v cc ramp (sample tested) symbol parameter min. max. unit f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 200 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter typ. max. unit trv cc v cc power?up rate .2 50 v/ms
x9430 ? preliminary information characteristics subject to change without notice. 14 of 21 rev 1.0 6/20/00 www.xicor.com dcp timing symbol table timing diagrams input timing symbol parameter min. max. unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/ sck edge (increment/decrement instruction) 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh
x9430 ? preliminary information characteristics subject to change without notice. 15 of 21 rev 1.0 6/20/00 www.xicor.com output timing hold timing dcp timing (for all load instructions) ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo ... cs sck si msb lsb vwx t wrl ... so high impedance
x9430 ? preliminary information characteristics subject to change without notice. 16 of 21 rev 1.0 6/20/00 www.xicor.com dcp timing (for increment/decrement instruction) write protect and device address pins timing ... cs sck so si addr t wrid high impedance vwx ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction)
x9430 ? preliminary information characteristics subject to change without notice. 17 of 21 rev 1.0 6/20/00 www.xicor.com applications information basic configurations of electronic potentiometers application circuits v r v w +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } }
x9430 ? preliminary information characteristics subject to change without notice. 18 of 21 rev 1.0 6/20/00 www.xicor.com application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 e g e +1/2 g o = 1 + r 2 /r 1 fc = 1/(2prc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 all r s = 10k ? + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o
x9430 ? preliminary information characteristics subject to change without notice. 19 of 21 rev 1.0 6/20/00 www.xicor.com packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 24-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 24 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0 ? 8 x 45
x9430 ? preliminary information characteristics subject to change without notice. 20 of 21 rev 1.0 6/20/00 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 0?8
x9430 ? preliminary information characteristics subject to change without notice. 21 of 21 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue prod uction and change specifications and prices at any time and without notice. xicor, inc. assumes no responsib ility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconducto r component failure may endanger life, system desi gners using this produc t should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor?s products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a ) are intended for surgical impl ant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?xicor, inc. 2000 patents pending rev 1.0 6/20/00 www.xicor.com ordering information device v cc limits blank = 5v 10% ?2.7 = 2.7 to 5.5v temperature range blank = commercial = 0 to +70c i = industrial = ?40 to +85c package s24 = 24-lead soic v24 = 24-lead tssop potentiometer organization pot 0 pot 1 w = 10k? 10k? x9430 p t v y

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